1. Field of the Invention
This invention relates to a semiconductor apparatus, and more particularly to a vertical semiconductor apparatus suitable for power electronics applications.
2. Background Art
The on-resistance of a vertical power MOSFET (metal-oxide-semiconductor field effect transistor) greatly depends on the electric resistance of its drift layer. The impurity concentration that determines the electric resistance of the drift layer cannot exceed a maximum limit, which depends on the breakdown voltage of the pn junction between the base and the drift layer. Thus there is a tradeoff between the device breakdown voltage and the on-resistance. Improving this tradeoff is important for low power consumption devices. This tradeoff has a limit determined by the device material. Overcoming this limit is the way to realizing devices with low on-resistance beyond existing power devices.
As an example MOSFET to solve this problem, JP-A 2000-277726 (Kokai) (hereinafter referred to as Patent Document 1) discloses a structure with p-type pillar layers and n-type pillar layers buried in the drift layer of the device region, which is known as a superjunction structure. In the superjunction structure, a non-doped layer is artificially produced by equalizing the amount of impurities contained in the p-type pillar layer with that contained in the n-type pillar layer. Thus, while holding a high breakdown voltage, a current is passed through the highly doped n-type pillar layer, realizing a low on-resistance beyond the material limit.
In a power device, in addition to the device region, the termination region also needs to hold a high breakdown voltage. As a structure for achieving a high breakdown voltage in the termination region, structures with a field plate, a RESURF (reduced surface field), or a field limited ring formed in the surface of the termination region are known. In these structures, a depletion layer can be extended toward the outside. However, excessive extension of the depletion layer to the surface and edge of the chip end results in decreased breakdown voltage, which is to be prevented. As an example structure for restricting the extension of the depletion layer, Patent Document 1 discloses a structure in which an n+-type stopper layer is provided in the surface of the chip end.
However, if the depletion layer is abruptly stopped by the stopper layer while it is insufficiently extended, a point of electric field concentration may locally occur. If a point of electric field concentration locally occurs in the termination region and causes the decrease of breakdown voltage, the device breakdown voltage is unfortunately determined by the termination breakdown voltage. Furthermore, because of the low termination breakdown voltage, the avalanche current concentrates exclusively on the termination section, also causing the device destruction.